Single Event Effect Measurements in 90nm CMOS Circuits at the Microbeam Facility for the Project FATAL

Final goal of the project FATAL is a simulation model which considers radiation induced effects, like single event transients (SETs) and single event upsets (SEUs), in asynchronous logic. Using this model, it will be possible to develop a design and simulation framework for designing radiation tolerant asynchronous logic. For synchronous logic such frameworks are already available. Synchronous logic is sensitive to single event effects (SEEs) at the clock edge only. Therefore it is sufficient to know the arising pulse widths of the SETs in order to design radiation tolerant synchronous logic [1]. In asynchronous logic there is no clock available. Thus it is sensitive to SEEs all the time. Furthermore, handshaking and data signals work with voltage transitions. Since SETs are nothing else than voltage transitions they can easily be misinterpreted as data or handshaking signals. To consider single event effects in a simulation model for asynchronous logic, it is necessary to know the exact shape of the arising SETs and the propagation of these pulses through the circuitry.